This invention relates to a manufacturing process for a semiconductor device. Further, the invention relates to the formation of a semiconductor device that contains gate structures. In particular, the invention relates to the formation of a silicon nitride layer on top of a gate oxide film, as part of a gate structure in a semiconductor device.
In the semiconductor industry, the continual shrinking of device size from product generation to product generation brings about many technical challenges in manufacturing semiconductor devices. One such challenge pertains to the gate oxide film of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) devices. The gate oxide film is a layer of oxide sandwiched between the semiconductor substrate and the gate (transistor) structure. As device size shrinks, the thickness of the gate oxide also shrinks. However, at some point, the oxide becomes too thin to provide sufficient electrical insulation between the conductive materials in the gate and the underlying semiconductor substrate. Also, a thinner gate oxide film is more susceptible to having implanted dopant ions diffuse into the gate oxide. These results can lead to performance issues with the transistor, as well as with the overall device.
Nitridation, the process of forming a gate insulating layer having a silicon nitride layer on top of the gate oxide, is one technology that has been developed to address such performance issues. A gate oxide film with a thin silicon nitride top layer can possess greater electrical insulative ability than a gate oxide film of the same thickness that has no silicon nitride top layer. In addition, a silicon nitride top layer provides resistance to the diffusion of dopants into the gate oxide.
One method of nitridation is decoupled plasma nitridation (DPN). The nitride film grown by DPN serves as an implant barrier so that, in subsequent ion implantation steps, dopants are prevented from migrating into the bulk of the gate oxide in the gate insulating layer during subsequent thermal processing steps. This also serves to preserve the insulating properties of the gate insulating layer and prevent electrical performance issues. As a result, DPN has become a useful process step in manufacturing semiconductor devices at and below the 60 nm technology threshold.
Nitridation processes, such as DPN, can be employed in the formation of surface p-channel MOSFET devices. Boron is a common dopant used to form p+ polysilicon gate structures in surface p-channel MOSFET devices. Performing DPN on the gate oxide film of a p+ polysilicon gate structure, which results in formation of a gate insulating layer, can help prevent boron implantation into the bulk of the gate oxide in the gate insulating layer.
However, DPN increases an interface charge between the gate insulating layer and the conductive material on top of the gate insulating layer. Often, this conductive material is a layer of polysilicon. DPN may also shift the flat band voltage of the device and induce negative bias temperature instability (NBTI) degradation.
Compounding these issues, DPN can be difficult to rework. This is because it may not be possible to remove a silicon nitride layer and recreate a silicon nitride layer with the required nitrogen content without permanently damaging the underlying gate insulating layer or other structures on the semiconductor substrate. As a result, semiconductor wafers that are subjected to an incomplete or otherwise incorrect DPN process may have to be discarded as scrap. Such wafers could otherwise result in compromised or nonfunctional devices if allowed to complete processing.
Inserting an anneal process after nitridation but before the next step in the manufacturing sequence, often polysilicon deposition, can address issues such as a shift in the flat band voltage and negative bias temperature instability (NBTI) degradation. Post-nitridation anneal, or PNA, chemically reduces meta-stable silicon-oxygen bonds in the gate oxide of the gate insulating layer and thus improves boron penetration resistance. A known method of PNA in the industry involves exposing wafers to nitrogen gas (N2) during the annealing process.
An additional issue that may arise with the use of DPN is that nitrogen decay occurs over time after the DPN process is complete. The concentration of nitrogen in the silicon nitride layer comprising the top of the gate insulating layer decreases with time, and this ultimately results in a change in the threshold voltage (Vt) of the gate structure. PNA can be beneficial in addressing this problem, but even after an N2-based PNA process, a detrimental nitrogen loss (0.5%) can occur approximately four hours after the DPN process finishes. This amount of decay can result in weaker Si—N bonds and therefore decreased protection from the penetration of implanted boron into the gate oxide of the gate insulating layer. This decreased protection in turn causes a Vt shift of 15-25 mV for a PMOS (p-channel metal oxide semiconductor) device. Thus, in a manufacturing environment, it is advisable to maintain a strict queue time of no more than four hours between the end of the DPN process and the beginning of the next step, polysilicon deposition. Once polysilicon is deposited, nitrogen decay from the silicon nitride layer of the gate insulating layer can no longer occur. The PNA process should therefore be performed within this queue time window to avoid unnecessary nitrogen decay.
However, it may be difficult in the manufacturing environment to perform a PNA step within this four-hour queue time window, especially when a furnace-type machine is used for the polysilicon deposition. DPN typically has a lower wafer per hour capacity than the polysilicon deposition process. An exemplary DPN process accommodates about 20.4 wafers/hour, while an exemplary polysilicon deposition processes four lots at once, with 25 wafers per lot. This means 100 wafers would have to leave the DPN equipment, complete PNA, and be ready for polysilicon deposition within four hours.
Alternatives to N2-only PNA have been explored. For example, U.S. Published Patent Application No. 2003/0170956 to Zhong et al. (“Zhong”) discloses a 4:1 mixture of N2:O2 being introduced in the annealing process. However, this process is performed in a furnace-type machine and therefore not in situ with the DPN process, which occurs in a chamber-type machine prior to the annealing process. Further, it is disadvantageous to have two sequential process steps respectively requiring two pieces of machinery within a short queue time window. For example, the two pieces of equipment may be spread across a large fabrication area and not adjacent to one another. In addition, semiconductor equipment often has an internal buffer of lots scheduled for processing ahead of any new lot that enters. Moreover, Zhong discloses that the N2:O2 process runs between 60 and 150 minutes, further challenging the queue time.
N2O-only PNA has also been tested, and has demonstrated a lower nitrogen decay rate than N2-only PNA, but a silicon nitride layer treated with N2O-only PNA has about half the initial percentage of nitrogen present as does a layer treated with N2-only PNA. Both N2-only and N2O-only PNA reduce interface charge to about the same extent. However, the shift in flat band voltage is much more pronounced for N2O-only PNA, and this can be detrimental to the performance of the semiconductor device. Thus neither N2-only nor N2O-only PNA may entirely address the above mentioned problems of the prior art.